Field of the Invention
The present invention relates to a semiconductor package structure, and in particular to a multi-die semiconductor package structure and methods for forming the same.
Description of the Related Art
With the continued development of electronics industries, such as those related to the 3Cs (Computer, Communications and Consumer electronics), there has been rapidly increasing consumer demand for devices that are multi-functional, more convenient, and smaller. This demand has driven the need for increased integrated circuit (IC) density. Increased input-output (I/O) pin count and increased demands for IC density have led to the development of multi-die packages. With demands for high performance and high integration, a dual-dies fan-out wafer level chip scale package (WLCSP), through silicon via (TSV) technology and a three-dimensional package on package (3D PoP) structure, have been accepted as some alternative choices.
However, a dual-dies fan-out WLCSP includes two dies disposed side by side. Accordingly, the size of the package is too big and warpage is an issue of concern. TSV technology comprises forming TSVs penetrating multiple dies. Accordingly, the fabrication cost is high and it wastes the area of the dies. A 3D PoP structure stacks a top package on a bottom package. Accordingly, it is difficult to reduce the thickness of the 3D PoP structure even further.
Therefore, a novel semiconductor package structure and methods for forming the same are desirable.